Intel Strengthens EMIB Packaging with Enhanced EDA Tool Enabling
The EMIB technology is designed to address the rising complexity in heterogeneously integrated multi-chip architectures. EMIB provides integrated IC packaging solutions for a range of integration technologies such as 2.5D and 3D IC. This was reported by SSPDaily.
During DAC, Intel highlighted collaborations with key EDA (Electronic Design Automation) and IP partners to ensure complete enablement and qualification of their design tools, methodologies, and reusable IP blocks to support EMIB assembly technology.
A crucial aspect of these collaborations was Intel Foundry's Package Assembly Design Kit (PADK). PADK enables engineers to create EMIB-based package designs while effectively addressing chip design complexity. This Kit comprises a design guide, rules, and stack-up that allow chip designers to efficiently complete and verify EMIB designs. Its implementation promotes EDA tool enablement and fosters effective EMIB-based assembly verification.
Intel has been establishing collaborative relationships with major EDA vendors for EMIB enablement. Let's take a closer look at these partnerships:
1. Siemens EDA
At DAC 2024, Siemens EDA announced tool certifications for EMIB enablement. The certifications include Solido SPICE, a component of the Solido Simulation Suite software, which will help design highly complex ICs. This certification is applicable for Intel's 16 and 18A process nodes.
In February 2024, Siemens EDA had already unveiled the availability of the EMIB reference flow, enabling early package assembly prototyping, device floorplanning, co-design optimization, and complete detailed implementation verification. The reference flow, which integrates Intel Foundry's PADK, empowers engineers to successfully tackle various critical tasks in design and tape-out processes.
2. Synopsys
Synopsys demonstrated a multi-die reference flow for Intel Foundry during DAC 2024. This reference flow employs Synopsys.ai EDA suite to offer designers a comprehensive and scalable solution for fast heterogeneous integration using EMIB assembly technology.
The reference flow, backed by Synopsys 3DIC Compiler, provides a consolidated co-design and analysis solution for expediting the development of multi-die designs from silicon to systems. Integration with Synopsys 3DSO.ai enables optimization for signal, power, and thermal integrity.
Ansys, currently in the process of being acquired by Synopsys, is also contributing with its electrothermal tools. Its offerings include multi-physics signoff solutions for Intel's 2.5D chip assembly technology, which utilizes EMIB to flexibly connect die without through-silicon vias. Ansys' RedHawk-SC Electrothermal EDA platform facilitates multi-physics analysis of 2.5D and 3D ICs with multiple dies.
3. Cadence Design Systems
Cadence has teamed up with Intel Foundry to certify an integrated advanced packaging flow that utilizes EMIB to address the mounting complexity in heterogeneously integrated multi-chip architectures. This flow allows design teams to smoothly transition from early-stage system-level planning, optimization, and analysis to DRC (Design Rule Check)-aware implementation and physical signoff without the need for format conversion.
These collaborations with EDA vendors enable efficient EDA tool adoption and integration into Intel's PADK. With the adoption of advanced packaging technologies like EMIB, Intel has pushed the boundaries of packaging technology development. Incorporating a comprehensive suite of EDA tools will empower chip designers to effectively implement and verify EMIB designs.
